Economic Observer reporter Zheng Chenye

On the morning of May 25th, at the 2026 International Circuit and System Symposium held in Shanghai, He Tingbo, Director and President of the Semiconductor Business Department of Huawei, officially delivered the "Tao (τ) Law" in his keynote speech titled "Exploration and Practice of Semiconductor New Paths". In circuit theory, τ represents the time constant, which is the time required for a signal to switch from one state to another.

Tao's Law proposes using "time microfabrication" instead of "geometric microfabrication" as a new guiding principle for the evolution of semiconductor and electronic systems. Through innovative technologies such as logical folding, the signal propagation delay is continuously compressed, and the transistor density is continuously increased to achieve the continuous evolution of semiconductor and electronic systems.

In recent years, Moore's Law has faced dual challenges of physical limits and economic benefits. As the "geometric miniaturization" of transistors slows down and the cost dividend gradually diminishes, how to overcome the limitations of traditional process paths and explore a new sustainable evolution path to meet the exponentially increasing demand for computing performance has become a common challenge that the global semiconductor industry urgently needs to overcome. Huawei claims that Tao's Law is an effective path to solving this problem.

Tao's Law constructs a multi-level collaborative optimization system that runs through the device, circuit, chip, and system levels. The system aims to systematically reduce the time constant τ and drive continuous improvement in performance, energy efficiency, and transistor density at all levels. Huawei expects that by 2031, the transistor density of high-end chips based on this law will reach the same level as the 1.4 nanometer process.

Affected by the "Huawei releases Tao's Law" incident, the Sci Tech Innovation 50 Index surged 5.88% on that day, reaching a new historical high.

Semiconductor industry chain companies surged in bulk: SMIC (688981. SH) closed up 18.78%, with a total market value of 1.25 trillion yuan; Huahong Company (688347. SH) closed up 20%; Shengmei Shanghai (688082. SH) closed up 17.75%; Tuojing Technology (688072. SH) closed up 16.86%; Huada Jiutian (301269. SZ) closed up 15.04%; Ganlun Electronics (688206. SH) closed up 13.19%; Zhaoyi Innovation (603986. SH) closed up 10%; Changdian Technology (600583. SH) closed up 10%; Cambrian (688256. SH) closed up 9.37%

So, how much will Tao's Law affect the development of the semiconductor industry?

From "shrinking size" to "pressing time"

The core of Tao's Law is actually not difficult to understand - the continuous improvement of chip performance no longer relies solely on making transistors smaller, but can be achieved through systematically compressing the propagation time of signals at various levels of the chip.

In his speech, He Tingbo stated that in the past six years (May 2020 to May 2026), Huawei has designed and mass-produced 381 chips based on this route, covering mobile AI、 Multiple fields such as automobiles and industry. The new generation Kirin chip, which will be released this autumn, will first adopt the core technology she highlighted in her speech - Logic Folding.

The product director of a semiconductor company in Shenzhen told the Economic Observer that the release of Tao's Law means that the design concept of integrated circuits in China is undergoing a transformation, shifting from simply pursuing smaller process nodes to multi-layer three-dimensional design with advanced packaging as the core.

On the same day, the preprint of He Tingbo's signed academic paper A Time Scaling Theory for Multi Layer Electronic Systems was released in ChinaXiv (the pre release platform of scientific and technological papers of the Chinese Academy of Sciences) and has been submitted to Science in China: Information Science.

This paper fully elaborates on the theoretical framework of Tao's Law, the process parameters of logical folding, and the measured performance data of Kirin 2026 chip. In his paper, He Tingbo stated that after Huawei faced the problem of "geometric miniaturization" six years ago, the entire industry will eventually face the question of how to continue improving chip performance.

Tao's Law provides an alternative path that has been validated through mass production, but the aforementioned paper also lists a series of unresolved technical challenges, ranging from EDA (Electronic Design Automation) toolchains to energy consumption control.

The so-called 'geometric miniaturization' is related to Moore's Law. In 1965, Intel co-founder Gordon Moore noticed a pattern: the number of transistors that can be accommodated on an integrated circuit doubles approximately every two years. This rule later became known as Moore's Law, which states that as transistors become smaller, more components can be packed into the same area of chip, resulting in improved performance while decreasing costs.

This method of improving chip performance by continuously reducing the physical size of transistors is known as "geometric miniaturization" in the industry. In the past 60 years, the technological iteration, capital investment, and product pricing of the global semiconductor industry have been largely based on this logic.

Moore's Law has been able to dominate the semiconductor industry for so long, and there are supporting theories behind it. In 1974, IBM engineer Robert Dennard proposed a scaling rule: the size and voltage of transistors can be proportionally reduced while maintaining the same power density. The significance of this rule is that it makes "reducing size" almost a side effect free thing. As the size shrinks, the speed increases, and due to the synchronous decrease in voltage, the power consumption per unit area does not increase, and the chip does not become hotter because of the increase in speed.

The entire semiconductor industry has entered a golden age of 'doing small is doing well'.

But this set of rules faced expiration around 2005.

The premise for the establishment of the Denard rule is that the voltage and size are synchronously reduced while the power consumption density remains unchanged. But after the voltage is reduced to a certain extent, the transistor begins to leak when it is turned off, and the side effect of "shrinking size" occurs: the chip's power density increases and heating intensifies. So, engineers in the chip industry had to activate only a portion of the chip at the same time, leaving the remaining transistors idle. This phenomenon is known as "dark silicon" in the industry. This also means that 'downsizing' is no longer automatically equivalent to 'comprehensive progress', and power consumption and heat generation have become additional costs for each generation of processes.

Although the premise of 'doing small equals doing well' has been shaken, geometric microfabrication is still the only mature technological route in the entire industry, and there is no alternative solution in the short term. At the same time, the rapid popularity of consumer electronics products such as smartphones continues to demand higher requirements for chip miniaturization and low power consumption, and the industry has ample motivation to continue on this path.

To address power consumption issues, the industry has made a major upgrade in transistor structure - traditional transistors are designed flat, and when the size is reduced to a certain extent, the control of the gate (the component that controls the current on and off) over the channel decreases, leading to increased leakage; FinFET (FinFET), which began mass production around 2012, changed the channel from a planar structure to a three-dimensional fin like structure, and wrapped the gate in three layers to enhance control force and alleviate leakage.

With this generation of architecture upgrades, geometric miniaturization has continued for about a decade, but as it enters processes of 7 nanometers and below, the performance improvements brought about by further downsizing are rapidly narrowing.

Why does geometric miniaturization accelerate failure after 7 nanometers? He Tingbo gave three reasons in the aforementioned paper:

Firstly, due to the speed saturation effect, the relationship between the speed increase and size reduction of transistors has changed from quadratic to linear. In the early days, the channel length (the channel through which the current inside the transistor passes) was reduced by half, and the switching speed could be increased by nearly four times; When it reaches below 7 nanometers, it also shrinks by half, and the speed increase is only about twice. With the same reduction, the profit obtained is halved.

Secondly, the parasitic resistance and capacitance of the interconnect lines within the chip are increasingly dominating signal delay. The transistors on the chip need to be connected by metal lines, and the switching speed of the transistors themselves is already very fast. However, the delay caused by these connection lines has become the main factor slowing down the entire chip. That is to say, no matter how small the transistor is made, if the line delay cannot be reduced, the overall speed cannot be improved.

Thirdly, at the economic level, with the significant increase in mask costs, EUV (extreme ultraviolet lithography, currently the most advanced chip lithography technology) equipment depreciation, and design rule complexity, the design budget for a single chip at the 2 nanometer node has exceeded $1 billion. That is to say, the cost of a single transistor in advanced manufacturing processes has increased instead of decreased.

Each generation has more transistors and lower unit costs, which has been the foundation for the continuous expansion of investment in the semiconductor industry over the past few decades. However, when the cost of a single transistor no longer decreases with process progress, this logic no longer holds true.

This is also the core reason why the industry has repeatedly discussed the failure of Moore's Law in recent years.

The industry has explored alternative paths beyond geometric microfabrication in multiple directions, with Chiplets (breaking down a large chip into multiple functional modules and combining them together through advanced packaging technology) being one of the most focused directions. In addition, for Huawei, this issue came earlier and is more urgent - in 2019, due to geopolitical influences, Huawei was unable to continue using the most advanced overseas chip foundry services. In this situation, regardless of whether Moore's Law is invalid or not, Huawei is unable to continue along the path of geometric miniaturization.

In her paper, He Tingbo summarized this situation: "For companies that cannot obtain top-notch lithography equipment, the problem of limited development appears earlier, and the pressure on the industry is more severe." She also stated in her paper that this is not just Huawei's situation, but the fundamental problem that Huawei was forced to face six years ago. "Looking back, the entire industry will eventually have to face it.

Starting from May 2020, Huawei's semiconductor team spent six years searching for alternative paths in mobile SoC (System on Chip), AI accelerators, system interconnection, and packaging technology. The conclusion drawn by He Tingbo in the above paper is that the breakthrough lies not in finding the next generation of process technology or new transistor architectures, but in changing and optimizing the goals themselves.

In the past 60 years, the essence of the performance improvement of each generation of chips has been to compress the running time - the transistors have become smaller and the switching speed has become faster; The interconnection arrangement is denser, and the signal transmission path is shorter; Improved integration and fewer boundaries crossed by data - shrinking space is always just a means of compressing time.

Based on this judgment, Tao's Law establishes time itself as the core optimization indicator for chip iteration.

Τ (tau) is defined as the "characteristic time constant" that runs through four levels: transistor, circuit, chip, and system. It covers a range of 12 orders of magnitude, from picoseconds (trillionths of a second, a time scale for measuring transistor switching speed) to seconds (a time scale for data centers to complete a complete task). Under this framework, geometric microfabrication is no longer the only technical route, but one of the means to reduce τ.

Or in other words, in the past, the semiconductor industry evaluated whether a chip was advanced or not, mainly based on how many nanometers of process technology it used. However, Tao's Law proposed a different evaluation standard - regardless of the process technology used, the final measure is how long it takes for the signal to complete a complete operation in the chip.

Process technology is the means, shortening time is the goal. As long as time can be compressed and mature processes combined with three-dimensional design can be used, high-performance chips can also be made.

He Tingbo's paper provides an intergenerational iteration formula: the next generation's τ is equal to the current τ divided by a scaling factor α.

Unlike Moore's Law, which gives the whole industry a unified iterative rhythm, the scaling factor of Tao's Law varies from scenario to scenario: the mobile phone terminal with limited power consumption is about 1.3 times per year, the auto drive system is about 1.5 times, and the AI scenario can be up to 10 times per year due to the direct correlation between computing power and economic value. Different industries determine the iteration speed according to their own needs, rather than being led by a unified process route.

The first core technology for the implementation of Tao's Law is logical folding.

In processes below 7 nanometers, the delay generated by the metal lines connecting the transistors has exceeded the switching time of the transistors themselves, becoming the main factor limiting chip speed. Traditional chips lay all circuits on the same plane, and signals propagate horizontally along metal lines. The longer the line, the greater the delay; The performance limit of a chip often depends on the delay of the longest signal path, which is referred to as the "critical path" in the industry. Logical folding addresses this issue by splitting critical circuits into vertically stacked multi-layer chips, which are connected through hybrid bonding (a process that aligns and permanently connects two wafers with micrometer level precision). Signals can traverse vertically, significantly reducing the length of the wiring and lowering the delay of critical paths.

The product director of the aforementioned Shenzhen semiconductor company analyzed to the Economic Observer reporter that the specific approach of logic folding may be to separate the metal interconnection of the high-speed signal part in the chip onto a second wafer, with the main wafer responsible for core computing, and achieve 3D vertical interconnection between the two wafers through hybrid bonding. As a result, after the wiring space reserved for high-speed signal interconnection lines is freed up, the number of effective transistors that can be placed on the main wafer increases.

In the above-mentioned paper, He Tingbo released the measured data of 2026 Kirin chips: the transistor density increased from 155 million per square millimeter in the previous generation to 238 million per square millimeter, a single generation increase of 55%. Previously, achieving the same level of density improvement usually required three years of geometric miniaturization and a complete process upgrade; The core energy efficiency has increased by 41%, and the maximum clock speed has increased by nearly 13%. The CPU performance core clock speed has reached 3.1GHz, and the SRAM (Static Random Access Memory, a storage unit used for high-speed caching) has increased its operating clock speed by more than 40%; On a typical processor core, the number of clock buffers (circuit components responsible for allocating and synchronizing clock signals) is reduced by more than half, and the wiring length is reduced by about 30%.

The above data were obtained within fixed process nodes without using new photolithography processes.

The paper also announced the main frequency iteration plan for Kirin chips in the following years: the target for 2027 is 3.39GHz, the target for 2028 is 3.71GHz, and the target for 2029 is 4GHz; By 2031, the target for transistor density is to exceed 400 million per square millimeter.

According to information released by Huawei, this density level will "reach the same level as the 1.4nm process". Huawei's manufacturing process did not achieve 1.4 nanometers, which refers to the use of logic folding and other technologies to achieve transistor density comparable to traditional 1.4 nanometer processes without relying on the most advanced photolithography processes.

It is worth mentioning that Tao's Law is not limited to mobile phone chips. More than 80% of the energy consumption of large AI clusters is used for data transmission, and over 70% of the cost is invested in storage devices. For AI systems, the transmission time of compressed data between chips, cabinets, and within packages is equally important as optimizing computation itself. He Tingbo also proposed multiple technical solutions for AI data centers in the above-mentioned paper.

According to He Tingbo's prediction in his paper, the integration of AI hardware will increase by more than 100 times by 2035. The Ascend series AI chips are expected to introduce logic folding technology around 2030.

A new round of demand for advanced packaging

Whether Tao's Law can be extended from a single chip to the entire industry depends on the maturity of a key process - advanced packaging.

A semiconductor industry chain analyst told Economic Observer that the release of Tao's Law marks the official systematic investment of domestic semiconductors in hybrid bonding and 3D stacking, which has a direct impact on wafer fabs, packaging companies, and EDA companies.

The core process of logical folding is to vertically stack two or even multiple wafers together. For every additional layer stacked, a complete manufacturing process is required: mixed bonding aligns and connects wafers with micrometer level precision; TSV (Through Silicon Via) creates vertical conductive channels on the wafer, allowing signals from the upper and lower layers to pass through; CMP (chemical mechanical polishing) grinds the surface of the wafer to nanometer level flatness, otherwise the bonding may not be accurate.

The aforementioned analyst told the Economic Observer that the logical folding route means multiple layers, multiple photolithography, thin film deposition, masking, and cleaning processes, which increases the demand for semiconductor equipment and materials. "Stacking two layers requires nearly twice as much equipment and materials as the flat solution, and stacking three layers requires even more.

He also stated that Tao's Law and Moore's Law are not interchangeable. The two routes each have one end, with Moore's Law managing spatial density and Tao's Law managing time efficiency. Ultimately, they all need to return to the basic manufacturing processes of photolithography, deposition, masking, and cleaning. The best solution is for both routes to go hand in hand.

The stock price trend of related semiconductor listed companies on the A-share market on May 25th basically reflects this transmission logic. For example, SMIC is currently the wafer foundry company in China that is closest to mass production capability in advanced processes, with its stock price skyrocketing by 18.78%; Huada Jiutian is one of the major EDA software manufacturers in China, with a stock price increase reaching the upper limit of 20%; Tuojing Technology is a major domestic manufacturer of thin film deposition and bonding equipment, with a stock price increase of up to 16.86%; Shengmei Shanghai is a semiconductor cleaning and electroplating equipment manufacturer, and its stock price has also surged by 17.75%.

However, He Tingbo also clearly listed a series of technical difficulties that Tao's law has not yet solved in his paper.

The first challenge is the EDA toolchain. The existing chip design software is developed for the flat era, optimizing the three indicators of area, timing, and power consumption separately. However, logic folding requires design tools to treat multi-layer stacked wafers as a whole and support cross layer allocation at the level of standard cells (the most basic logic functional units in chip design). Traditional 2D design tools cannot meet this requirement.

In his paper, He Tingbo stated that Huawei has developed a preliminary internal toolchain, and the methodological details will be publicly released in the future. She referred to the open-source EDA toolchain for tau scaling as the 'most essential foundational investment for the next decade'.

The second challenge is the process deviation between wafers. Logical folding requires bonding wafers from different batches or even different process nodes together, but the electrical parameter differences between different wafers are much greater than the differences within the same wafer, which puts great pressure on the distribution of clock signals and timing margins (the time margin required for the circuit to function normally).

He Tingbo also mentioned an easily overlooked issue in his paper: τ is a time criterion, not an energy consumption criterion. For example, if a system runs 10 times faster and its power consumption also increases by 10 times, theoretically it does not violate Tao's law, but in actual deployment it will exceed the carrying capacity of the power system. So, she also explicitly stated in her paper that Tao's Law must be accompanied by a complete energy consumption optimization system in order to be implemented in products.

In addition, the existing performance evaluation standards in the chip industry, such as Linpack, MLPerf, and SPEC (three widely used benchmark tests for computing performance), are designed to measure a single indicator and cannot evaluate the full stack collaborative optimization effect pursued by Tao's Law.

In his paper, He Tingbo called on the industry to establish a new benchmark testing system that can quantify the delay distribution and optimization space at all levels of the system.

It is worth mentioning that He Tingbo also stated at the end of the paper, "What needs to be done in the next decade is clear. There are still a lot of problems that have not been solved, and no single enterprise can deal with them alone. The toolchain, industry standards, benchmark testing, device physics, and economic models all require joint contributions from the entire industry. This paper is both a report from the front line of practice and an invitation letter. The road ahead is full of challenges, but the direction is clear and definite